The present invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device having clock wiring with reduced clock skew.
Some semiconductor integrated circuit devices, such as VLSIs, include a synchronous circuit having flip-flops driven by a common clock signal. To make such a synchronous circuit operate more rapidly, these semiconductor integrated circuit devices require that clock skew (i.e, differences in clock supply timing between flip-flops) be minimized for removal of signal-to-signal timing differences.
Various layout design techniques for reducing such clock skew have been proposed. One such technique involves installing tree-structure paths between a clock signal generator and a plurality of flip-flops, where in the length of the path between the generator and each flip-flop is suitably adjusted. Another technique, which is disclosed in Japanese Published Unexamined Patent Application No. Hei 9-307069, requires inserting clock buffers where appropriate when tree-structure wiring has been established, whereby the tree structure is readjusted so that the difference between a maximum and a minimum of delays on the readjusted wiring attains a predetermined value. Where there still remains clock skew despite the provision of tree structure wiring, another technique disclosed in Japanese Published Unexamined Patent Application No. Hei 8-274260 seeks to minimize the skew by replacing appropriate drivers with small-capacity drivers so that the paths with maximum skew become equal in skew level to other tree branch paths between second stage clock drivers and block circuits.
The conventional techniques outlined above have failed to consider optimum arrangements of skew reduction for VLSIs. These techniques presuppose that on tree-structure paths between a clock generator and each flip-flop, each node is afforded wiring of an equal length. If equal-length wiring is provided ranging from a clock generator through a plurality of stages of drivers to flip-flops, alternative lines necessitated by the equal-length lines at all stages prolong the overall clock wiring. The resulting disadvantages include more delays of clock signals and higher power dissipation.
Furthermore, the conventional techniques above have disregarded an optimum clock layout for each of the functional portions or for each of a plurality of clock phases in connection with LSIs. A VLSI comprises random logic circuits and data paths reflecting various functions of the device, as well as numerous I/O pads. The conventional techniques have so far shied away from providing any optimum clock layout for the diverse internal arrangements of the LSI.
It is therefore an object of the present invention to provide a semiconductor integrated circuit device having a clock skew-lowering layout that ensures reduced wiring delays, enhanced packaging density and low clock power dissipation.
It is another object of the present invention to provide a semiconductor integrated circuit device having an optimum clock layout corresponding to each of the functional portions constituting an LSI.
These and other objects, features and advantages of the invention will become more apparent upon a reading of the following description and appended drawings.
Major features and benefits of the invention are outlined below. In carrying out the invention, and according to one aspect thereof, there is provided a semiconductor integrated circuit device comprising a plurality of stages of clock drivers furnished on clock wiring paths ranging from a clock generator to flip-flops. Clock lines connecting upper stage clock drivers have an equal length each in the form of a tree structure, and clock lines connecting lower stage clock drivers have the shortest possible lengths.
The lower the stage, the greater the number of clock drivers furnished. In that structure, clock lines connecting lower stage clock drivers are made to have not equal lengths but the shortest possible lengths. The arrangement shortens the overall clock wiring, reduces wiring delays, enhances packaging density, and lowers clock power dissipation. Since the lower stage clock drivers are connected by lines that are shorter than those connecting the upper stage clock drivers, the lower stage clock drivers may have the shortest possible wiring entailing negligible clock skew. Because the upper stage clock drivers are connected by extended wiring, the lines constituting such wiring are made to be equal in length in order to minimize clock skew.
A semiconductor integrated circuit device according to another aspect of the invention also comprises a plurality of stages of clock drivers. Of these drivers, intermediate stage clock drivers are provided with clock logic circuits for controlling clock signal supply.
The clock logic circuits control the supply of clock signals to individual function blocks corresponding to the intermediate clock drivers in question. The setup implements a clock signal supply scheme suitable for a VLSI while minimizing clock skew. Preferably, next-to-last stage clock drivers may have clock logic circuits for supply of clock signals to the flip-flops of random logic circuits and input/output pads, and both last stage and next-to-last stage clock drivers may have clock logic circuits for the supply of clock signals to the flip-flops of data paths.